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differential input, 555 ksps 12-bit adc in an 8-lead sot-23 ad7452 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features specified for v dd of 3 v and 5 v low power at max throughput rate: 3.3 mw max at 555 ksps with 3 v supplies 7.25 mw max at 555 ksps with 5 v supplies fully differential analog input wide input bandwidth: 70 db sinad at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface: spi?/qspi?/microwire?/dsp compatible power-down mode: 1 a max 8-lead sot-23 package applications transducer interface battery-powered systems data acquisition systems portable instrumentation motor control general description the ad7452 1 is a 12-bit, high speed, low power, successive approximation (sar) analog-to-digital converter that features a fully differential analog input. this part operates from a single 3 v or 5 v power supply and features throughput rates up to 555 ksps. the part contains a low noise, wide bandwidth, differential track-and-hold amplifier (t/h) that can handle input frequencies up to 3.5 mhz. the reference voltage is applied externally to the v ref pin and can be varied from 100 mv to 3.5 v depending on the power supply and what suits the application. the value of the reference voltage determines the common-mode voltage range of the part. with this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the device to interface with microprocessors or dsps. the input signals are sampled on the falling edge of cs , and the conversion is also initiated at this point. functional block diagram v ref t/h control logic 12-bit successive adc gnd sclk sdata cs v dd ad7452 v in+ v in? approximation 03154-a-001 figure 1. the sar architecture of this part ensures that there are no pipeline delays. the ad7452 uses advanced design techniques to achieve very low power dissipation. product highlights 1. operation with either 3 v or 5 v power supplies. 2. high throughput with low power consumption. with a 3 v supply, the ad7452 offers 3.3 mw max power consumption for 555 ksps throughput. 3. fully differential analog input. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. this part also features a shutdown mode to maximize power efficiency at lower throughput rates. 5. variable voltage reference input. 6. no pipeline delay. 7. accurate control of the sampling instant via a cs input and once-off conversion control. 8. enob > 8 bits typically with 100 mv reference. 1 protected by u.s. patent number 6,681,332.
ad7452 rev. b | page 2 of 28 table of contents ad7452Cspecifications .................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 te r m i no l o g y ...................................................................................... 8 ad7452Ctypical performance characteristics .......................... 10 circuit information ........................................................................ 13 converter operation .................................................................. 13 adc transfer function ............................................................. 13 typical connection diagram ................................................... 14 analog input ............................................................................... 14 driving differential inputs ........................................................ 16 digital inputs .............................................................................. 18 reference ..................................................................................... 18 single-ended operation ............................................................ 18 serial interface ............................................................................ 19 modes of operation ....................................................................... 20 normal mode .............................................................................. 20 power-down mode .................................................................... 20 power-up time .......................................................................... 21 power vs. throughput rate ....................................................... 22 microprocessor and dsp interfacing ...................................... 22 application hints ....................................................................... 24 evaluating the ad7452s performance .................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 2/04data sheet changed from rev. a to rev. b added patent note ....................................................................... 1 2/04data sheet changed from rev. 0 to rev. a updated formatting .......................................................universal changes to applications section................................................. 1 changes to general description ................................................ 1 changes to specifications ............................................................ 4 changes to timing specifications .............................................. 5 changes to timing example ..................................................... 19 9/03revision 0: initial version
ad7452 rev. b | page 3 of 28 ad7452Cspecifications v dd = 2.7 v to 3.6 v, f sclk = 10 mhz, f s = 555 ksps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 10 mhz, f s = 555 ksps, v ref = 2.5 v; v cm 1 = v ref a min max ; t = t to t , unless otherwise noted. table 1. parameter test conditions/comments b version 2 unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 3 70 db min total harmonic distortion (thd) 3 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max peak harmonic or spurious noise 3 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max intermodulation distortion (imd) 3 fa = 90 khz, fb = 110 khz second-order terms C89 db typ third-order terms C89 db typ aperture delay 3 5 ns typ aperture jitter 3 50 ps typ full power bandwidth 3 , 4 @ C3 db 20 mhz typ @ C0.1 db 2.5 mhz typ dc accuracy resolution 12 bits integral nonlinearity (inl) 3 1 lsb max differential nonlinearity (dnl) 3 guaranteed no missed codes to 12 bits 0.95 lsb max zero-code error 3 6 lsb max positive gain error 3 2 lsb max negative gain error 3 2 lsb max analog input full-scale input span 2 v ref 5 v in+ C v inC v absolute input voltage v in+ v cm = v ref v cm 1 v ref /2 v v inC v cm = v ref v cm 1 v ref /2 v dc leakage current 1 a max input capacitance when in track/hold 30/10 pf typ reference input v ref input voltage v dd = 4.75 v to 5.25 v (1% tolerance for specified performance) 2.5 6 v v dd = 2.7 v to 3.6 v (1% tolerance for specified performance) 2.0 7 v dc leakage current 1 a max v ref input capacitance when in track/hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 8 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v, i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v, i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 8 10 pf max output coding twos complement
ad7452 rev. b | page 4 of 28 parameter test conditions/comments b version 2 unit conversion rate conversion time 1.6 s with a 10 mhz sclk 16 sclk cycles track-and-hold acquisition time 3 sine wave input 200 ns max step input 290 ns max throughput rate 555 ksps max power requirements v dd range: 3 v + 20%/C10%; 5 v 5% 2.7/5.25 v min/v max i dd 9 , 10 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.5 ma max v dd = 2.7 v to 3.6 v 1.2 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v, 1.55 mw typ for 100 ksps 9 7.25 mw max v dd = 3 v, 0.64 mw typ for 100 ksps 9 3.3 mw max full power-down v dd = 5 v, sclk on or off 5 w max v dd = 3 v, sclk on or off 3 w max 1 common-mode voltage. the input signal can be centered on a dc common-mode voltage in the range specified in and . figure 23 figu re 24 2 temperature ranges as follows: b version: C40c to +85c. 3 see section. terminology 4 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time may cause a n incorrect result to be returned by the converter. 5 because the input spans of v in+ and v inC are both v ref and are 180 out of phase, the differential voltage is 2 v ref. 6 the ad7452 is functional with a reference input from 100 mv; for v dd = 5 v, the reference can range up to 3.5 v. 7 the ad7452 is functional with a reference input from 100 mv; for v dd = 3 v, the reference can range up to 2.2 v. 8 guaranteed by characterization. 9 see section. power vs. throughput rate 10 measured with a midscale dc input.
ad7452 r e v. b | pa ge 5 o f 2 8 timing spe c ific ations g u a r an t e ed b y c h a r ac t e r i za tio n . al l in p u t sig n a l s a r e s p ecif ied wi t h tr = tf = 5 n s (10% t o 90% o f v dd ) a n d t i me d f r o m a 1.6 v vol t a g e le vel. s e e f i gur e 2 a nd t h e s e r i a l i n ter f ace s e c t ion. v dd = 2.7 v t o 3.6 v , f sc l k = 10 mh z, f s = 555 ks ps, v ref = 2.0 v ; v dd = 4.75 v t o 5.25 v , f sc l k = 10 mh z, f s = 555 ks ps, v ref = 2.5 v ; v cm 1 = v ref a min max ; t = t to t , u n l e s s o t h e r w i s e n o t e d . table 2. parameter limit at t min , t ma x unit description f sclk 2 10 khz min 10 mhz max t con v ert 16 t sclk t sclk = 1/f sclk 1.6 s max t qu iet 60 ns min minimum quiet time between the end of a se rial read and the next falling edge of cs t 1 10 ns min minimum cs pulse wid t h t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 3 20 ns max delay from cs falling edge until s d ata three-state disabled t 4 3 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to da ta valid hold time t 8 4 10 ns min sclk falling edge to sdata three-state enabled 35 ns max sclk falling edge to sdata three-state enabled t power - up 5 1 s max power-up time from full power-down t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk sdat a 4 leading zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db11 db10 db2 db1 db0 b 03154-a - 002 f i g u re 2. s e r i a l i n te r f ac e ti m i ng d i ag r a m 1 common - m od e vo lt age. 2 mark/ s pace ratio for the sc lk input is 40/60 to 60/40. 3 mea s ure d with the loa d circuit o f a n d d e f i ne d as the time re quire d fo r the o u tput to cro s s 0.8 v or 2.4 v wi th v figu re 3 f i g ure 3. dd = 5 v, or 0.4 v or 2.0 v for v dd = 3 v. 4 t 8 i s d e ri ved f r om t h e m e a s ur ed t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v wh en loa d ed wi t h t h e ci rcui t o f th e m e a s ured numbe r i s the n extrapo l ate d back to re mo ve the e f f e cts of charging o r d i s c harging the 25 pf capacito r. this me ans that the ti me , t 8 , quoted in the timing specif icat ions is the true bus rel i nquis h time of the part and is in d e pe nde nt o f the bus lo ad ing. 5 se e s e ct i o n . powe r- up ti m e
ad7452 r e v. b | pa ge 6 o f 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v v in+ to gnd C0.3 v to v dd + 0.3 v v inC to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to +7 v digital output v o ltage to gnd C0.3 v to v dd + 0.3 v v ref to gnd C0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (b version) C40c to +85c storage temperature range C65c to +150c junction tempe r ature 150c ja thermal impedance 211.5c/w jc thermal impedance 91.99c/w lead temperature, soldering vapor phase (60 secs) 215c infrared (15 secs) 220c e s d 1 k v s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 transient currents of up to 100 ma wi ll not cau s e scr latch-up. 1.6ma i ol 200 ai oh 1.6v to output pin c l 25pf 03154-a - 003 f i gure 3 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7452 r e v. b | pa ge 7 o f 2 8 pin conf iguration and fu nction descriptions v dd 1 sclk 2 sdata 3 cs 4 v ref v in+ v in? gnd 8 7 6 5 03154-a-004 ad7452 top view (not to scale) f i g u re 4. 8-l e ad s o t - 23 pin conf ig u r at ion ta ble 4. pi n f u nct i on d e s c ri pt i o ns mnemonic function v ref reference input for the ad7452. an external refe rence must be applied to this in put. for a 5 v power supply, the reference is 2.5 v ( 1%) for specified perfor mance. for a 3 v power supply, the reference is 2 v ( 1%) for specified performa nce. this pin should be decoupled to gnd w i th a capacitor of at leas t 0.1 f. see the reference section for m o re details. v in+ positive terminal for differential analog input. v inC negative terminal for di fferential analog input. gnd analog ground. ground reference point for all circuitry on th e a d 7452. all analog input signa ls and any external reference signal should be referred to this gnd voltage. cs chip select. acti ve low logic input. this input pr ovides the dual function of initiating a conver si on on the ad7452 and framing the serial data transfer. sdata serial data. logi c output. the co nversion re sult from the ad7452 is provided on this output as a serial data stream. the bits are cloc ked out on the falling ed ge of the sc lk i n put. the data s t ream co nsists of four leading zero s fol l owed by the 12 bits o f conver sion data , which are pr ov ided msb firs t. t h e output coding is twos complement. sclk serial clock. log i c input. sclk provides th e serial clock for accessing data from the part. t h is cloc k input is als o used as th e clock source for the conversi on proces s. v dd power supply input. v dd is 3 v (+20%/C10%) or 5 v ( 5%). this supply shou ld be decoupled to gnd with a 0.1 f capacitor and a 10 f tantalum capa citor i n paral l el.
ad7452 r e v. b | pa ge 8 o f 2 8 terminology signal-to-(noise + distortion) ratio t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a d c. th e sig n al i s t h e r m s am pli t ude o f t h e f u n- d a m e n t al . n o i s e i s th e s u m o f all n o n f un d a m e n t al si gn als u p t o half th e s a m p ling f r e q uen c y (f s / 2 ), excl udin g dc. the ra t i o is dep e n d en t on t h e n u m b er o f q u a n t i za tion levels in the dig i tiza- ti o n p r oce s s; t h e m o r e lev e l s, th e sm alle r th e q u a n tiz a ti o n n o i s e . t h e t h e o re t i c a l s i g n a l - t o - ( n oi s e + d i stor t i on ) r a t i o f o r an i d e a l n- b i t con v er t e r wi t h a si ne w a ve in p u t is g i v e n b y sig n al - to -( n o i s e + d i s t or t i on ) = (6.02 n + 1.76) db th us, f o r a 12-b i t con v er t e r , this is 74 db . total harmoni c distortion (thd) t o t a l h a r m on i c d i stor t i on i s t h e r a t i o of t h e r m s su m of ha r m o n ics t o the f u ndam e n t al . f o r th e ad7452 , i t is def i n e d as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 ) db ( + + + + = wher e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t a l and v 2 , v 3 , v 4 , v 5 , a n d v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t o t h e sixt h h a r mon i c s . peak harmoni c or spurious noise p e a k ha r m o n ic o r sp ur io us n o is e is def i ne d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p u t sp e c t r u m ( u p to f s /2 an d excl udi n g dc) t o t h e r m s val u e o f t h e f u ndam e n t a l. n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is de t e r - mi n e d b y t h e l a rg es t ha r m o n ic in t h e sp e c t r um, b u t fo r ad cs wher e t h e ha r m o n ics a r e b u r i e d in t h e n o is e f l o o r , i t is a n o i s e peak . intermodulati o n distortion w i t h in p u ts co nsis t i n g o f sine wa v e s a t tw o f r e q uen c ies, fa and fb , a n y a c t i v e de v i ce wi th n o nlin ea ri ti e s cr e a t e s d i s t o r ti o n p r o- d u c t s a t t h e s u m an d dif f er en c e f r e q uen c ies o f mfa nfb w h er e m, n = 0, 1, 2, 3, a n d s o o n . i n t e r m o d u l a t ion disto r tio n t e r m s a r e th ose f o r wh ich n e i t h e r m n o r n a r e eq ual t o zer o . f o r exa m p l e , th e s e co n d -o r d er t e r m s in c l ude (fa + fb) a n d (fa ? fb), wh ile th e th ir d - o r d e r t e r m s in c l ud e (2fa + fb), (2fa ? fb), (fa + 2fb) a n d (fa ? 2fb). the ad7452 is t e s t e d usin g t h e ccif s t anda rd wher e tw o in p u t f r e q u e nc i e s ne a r t h e top e n d of t h e i n put b a nd w i d t h are u s e d . i n t h is c a s e , t h e s e con d -o r d er t e r m s a r e us ual l y dis t an c e d i n f r e q uen c y f r o m t h e o r ig inal sin e wa v e s w h ile t h e t h ir d-o r der t e r m s a r e us ual l y a t a f r e q ue n c y c l os e t o t h e in p u t f r e q uen c ies. a s a r e su lt, t h e s e co nd- and t h ird-o r der ter m s ar e sp e c if ie d se pa ra t e l y . th e c a l c ul a t i o n o f th e in t e r m o d ula t i o n d i s t o r ti o n i s as p e r t h e thd s p e c if ic a t ion w h er e i t is t h e ra t i o o f t h e r m s s u m o f th e in d i v i d u al d i s t o r ti o n p r od u c t s t o th e rm s a m p l i t u d e o f t h e s u m o f t h e f u ndam e n t a ls exp r es s e d i n db . ap erture dela y t h e a mou n t of t i m e f r om t h e l e a d i n g e d ge of t h e s a m p l i ng c l o c k un t i l t h e ad c ac t u al l y t a k e s t h e s a m p le . aperture jitter the s a m p le-t o- s a m p le va r i a t ion in t h e ef fe c t i v e p o in t i n t i m e a t w h ich t h e ac t u a l s a m p le is t a k e n. full power bandwidth the f u l l p o w e r b a ndwi d t h o f an a d c is t h e i n p u t f r e q uen c y a t which t h e a m pl i t ude o f t h e r e con s t r uc t e d f u ndam e n t a l is r e d u ced b y 0.1 db o r 3 db f o r a f u l l -s cale in p u t. commo n- mode rejection rat i o (cmrr) this is t h e ra t i o o f t h e p o w e r in t h e ad c ou t p u t a t f u l l -s ca le fr e q u e n c y , f , t o th e p o w e r o f a 100 mv p-p sin e wa v e a p p l ie d t o t h e comm o n - m o d e v o l t a g e o f v in+ an d v inC of f r e q u e nc y f s cmrr (d b) = 10 log( pf / pf s ) pf is t h e p o w e r a t t h e f r e q ue n c y f in t h e a d c ou t p ut; pf s is t h e po w e r a t f r eq u e n c y f s in t h e ad c o u t p ut. in tegral non l i n earity (inl) the maxi m u m de v i a t ion f r o m a st ra ig h t li n e p a ssin g t h r o ug h t h e e n d p oin t s of t h e a d c t r a n s f er f u n c t i o n . differe ntial no nlinearity (dn l ) the dif f er ence b e tw e e n t h e m e as ur e d and t h e i d e a l 1 ls b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . zero code err o r the devia t ion of th e mids cale c o de tra n si t i o n ( 111111 t o 000...000) f r o m th e ideal v in+ C v inC (i .e ., 0 ls b)
ad7452 rev. b | page 9 of 28 positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal v in+ C v inC (i.e., v ref C 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal v in+ C v inC (i.e., Cv ref + 1 lsb), after the zero code error has been adjusted out. track-and-hold acquisition time the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the ratio of the power in the adc output at full-scale fre- quency, f , to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of this input varies from 1 khz to 1 mhz. psrr (db) = 10log( pf / pf s ) pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output.
ad7452 rev. b | page 10 of 28 ad7452Ctypical performance characteristics t a = 25c, f s = 555 ks ps, f sc l k = 10 mh z, unles s o t h e r w is e n o ted . frequency (khz) 10 100 s i nad (db) 65 60 55 277 70 75 v dd = 4.75v v dd = 3.6v v dd = 2.7v v dd = 5.25v 03154-a - 005 f i g u re 5. sina d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es frequency (khz) 10 100 cmrr (db) ?100 10000 0 1000 v dd = 3v v dd = 5v ?9 0 ?8 0 ?70 ?60 ?50 ?40 ?30 ?20 ?1 0 03154-a - 006 fi g u r e 6 . c m r r v s . fr e q u e n c y f o r v dd = 5 v a n d 3 v supply ripple frequency (khz) 0 100 200 300 400 500 p s rr (db) ?120 900 1000 0 v dd = 5v v dd = 3v ?100 ?8 0 ?6 0 ?4 0 ?2 0 100mv p-p sine wave on v dd no decoupling on v dd 600 700 800 03154-a - 007 f i g u r e 7 . p s r r v s . s u pp l y ripp le f r e q ue n c y w i t h o u t s u pp ly de c o u p l i n g frequency (khz) 0 100 200 s nr (db) ?100 ?140 277 ?2 0 0 ?120 ?4 0 ?6 0 ?8 0 8192 point fft f sample = 555ksps f in = 100ksps sinad = 71.7db thd = ? 82db sfdr = ? 83db 03154-a - 008 f i gure 8. d y na mi c p e r f o r m a nce w i th v dd = 5 v ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl e rror (ls b ) code 1024 0 2048 3072 4096 03154-a - 009 f i gure 9. t y pic a l d n l for v dd = 5 v ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl e rror (ls b ) code 1024 0 2048 3072 4096 03154-a - 010 f i gure 10. t y pic a l i n l for v dd = 5 v
ad7452 rev. b | page 11 of 28 v ref (v) 1.5 0 0.5 1.0 1.5 2.0 2.5 change in dnl (ls b ) 1.0 0.5 0 ?0.5 ?1.0 3.0 3.5 2.0 2.5 3.0 positive dnl negative dnl 03154-a - 011 f i gure 1 1 . change in dnl vs . v ref fo r v dd = 5 v v ref (v) 1.5 0 0.5 1.0 1.5 2.0 2.5 change in dnl (ls b ) 1.0 0.5 0 ? 0.5 ? 1.0 2.0 2.5 positive dnl negative dnl 2.2 03154-a - 012 f i gure 1 2 . change in dnl vs . v ref fo r v dd = 3 v v ref (v) 0 0 0.5 1.0 1.5 2.0 2.5 change in inl (ls b ) ?1 ?2 ?3 ?4 ?5 3.0 3.5 1 2 3 positive inl negative inl 4 5 03154-a - 013 f i gure 1 3 . change in inl vs . v ref for v dd = 5 v v ref (v) 1.0 0 0.5 1.0 1.5 2.0 change in inl (ls b ) 0.5 0 ?0.5 ?1.5 ?2.0 1.5 2.0 positive inl nega tive inl 2.2 2.5 03154-a -014 f i gure 1 4 . change in inl vs . v ref for v dd = 3 v v ref (v) 5 0 0.5 1.0 1.5 2.0 2.5 ze ro-code e rror (ls b ) 4 3 2 1 0 3.0 3.5 6 7 8 v dd = 5v v dd = 3v 03154-a - 015 f i gure 15. cha n ge i n zero - c ode e r ror v s . r e fer e nce v o ltag e v dd = 5 v and 3 v v ref (v) 9.5 0 0.5 1.0 1.5 2.0 2.5 e ffe ctiv e numbe r of bits 9.0 8.5 8.0 7.5 7.0 3.0 3.5 10.0 10.5 11.0 v dd = 3v v dd = 5v 11.5 12.0 03154-a - 016 f i gure 1 6 . change in enob vs . re fe r e nc e v o l t a g e v dd = 5 v and 3 v
ad7452 rev. b | page 12 of 28 code 8,000 7,000 4,000 0 5,000 9,000 3,000 10,000 2,000 1,000 6,000 2044 2046 2047 2048 2049 2045 10,000 codes v in+ = v in? 10,000 conversions f s = 555ksps 03 15 4- a - 01 7 f i g u re 17. h i s t og r a m of 1 0 ,0 0 0 conver s i ons of a dc input wit h v dd = 5 v
ad7452 rev. b | page 13 of 28 circuit i n formation the ad7452 is a 12-b i t, lo w p o w e r , sin g le-s u p pl y , s u cces s i v e a p p r o x ima t io n a n alog-t o-d i g i ta l co n v er t e r (ad c ). i t ca n o p era t e wi t h a 5 v o r 3 v p o w e r s u p p ly , a n d is c a p a b l e o f thr o ug h p u t ra t e s u p t o 555 ks p s when su p p lie d wi th a 10 m h z s c l k . i t re qu i r e s an e x te r n a l re f e re nc e to b e a ppl i e d to t h e v ref p i n, wi t h t h e value o f t h e r e fer e n c e ch os e n de p e ndin g on t h e p o w e r s u p p l y a n d w h at s u i t s t h e ap p l i c at i o n . w h en o p era t e d wi t h a 5 v s u p p ly , t h e maxi m u m r e fer e n c e t h a t ca n b e a p plie d i s 3.5 v . w h en op era t e d wi t h a 3 v s u p p ly , t h e max i m u m r e fer e n c e t h a t can b e a p plie d is 2.2 v ( s e e t h e refer e nce s e c t i o n) . the ad7452 has a n o n -c hi p dif f er en tial track-and-h o ld a m plif ier , a succ essi v e a p p r o x ima t io n (s ar) a d c, a n d a s e r i a l in t e r f ace , h o us e d in a n 8-lead s o t - 23 p a c k a g e . the s e r i al c l o c k in p u t acces s es da t a f r o m t h e p a r t a n d p r o v ides t h e clo c k s o ur ce f o r th e s u cces s iv e a p p r o x ima t ion ad c. th e ad7452 f e a t ur es a p o we r - d o w n opt i on f o r re d u c e d p o we r c o nsu m pt i o n b e t w e e n co n v ersio n s. the p o w e r - do wn fe a t ur e is im ple m e n t e d acr o s s t h e st anda r d s e r i a l i n ter f ace as des c r i b e d i n t h e m o des o f o p er a t ion secti o n . converter operation the ad7452 is a s u cces s i v e a p p r o x ima t ion ad c bas e d a r o u n d tw o c a p a ci ti ve d a cs. f i gur e 1 8 a n d f i gur e 19 s h o w sim p lif i ed s c h e ma t i c s o f t h e ad c in t h e acq u isi t io n an d c o n v ersio n phas e, r e s p ec ti v e l y . the ad c is co m p r i s e d o f co n t r o l l o g i c, a n sar , a n d tw o ca p a c i t i v e d a cs. i n f i gur e 18 (acq uisi tio n p h as e), sw3 is clos e d an d s w 1 an d s w 2 a r e in p o si t i on a, t h e com p a r a t o r is hel d i n a b a l a nc e d c o nd it i o n , an d t h e s a m p l i ng c a p a c i tor ar r a y s acq u ir e t h e dif f er en t i a l sig n al on t h e in p u t. v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03154-a - 018 f i g u re 18. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 19), sw3 o p e n s an d sw1 and sw2 m o v e t o p o si t i on b , c a usin g t h e co m p a r a t o r t o b e come un b a lan c e d . b o t h i n p u ts ar e dis c o n ne c t e d on ce t h e co n v ersio n b e g i n s . th e co n t r o l log i c a n d t h e c h a r g e r e dis t r i b u - t i on d a c s are u s e d to a d d a n d s u bt r a c t f i x e d a mou n t s of ch ar ge f r o m th e sam p lin g ca paci t o r a r ra ys t o b r in g t h e co m p a r a t o r bac k in t o a b a lan c e d co n d i t io n. w h en t h e co m p a r a t o r is r e bala nced , t h e co n v ersio n is com p let e . the co n t r o l log i c g e n e r a t e s t h e a d c s o u t p u t c o de . th e o u t p u t i m p e dances o f t h e s o ur ces dr i v ing t h e v in + and t h e v inC pi ns m u s t b e m a tc he d ; o t h e r w is e , t h e t w o in p u t s wi l l ha v e dif f er en t s e t t lin g t i m e s, re su lt i n g i n e r ror s . v in+ v in? a b sw1 sw3 control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03154-a - 019 comparator f i g u re 19. a d c co nvers i on p h as e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad74 52 is tw os co m p lem e n t . th e desig n e d co de t r a n si t i o n s o c c u r a t s u cces s i v e ls b val u es (i .e ., 1 ls b , 2 ls bs, a n d s o o n ). the ls b si ze is 2 v ref /4096. the ideal tran sf er c h a r ac t e r i s t ic o f th e ad7452 is s h own in f i gur e 20. 100...000 ?v ref ad c co de analog input (v in+ ?v in ? ) 011...111 100...001 000...000 000...001 111...111 1lsb + v ref ? 1lsb 1lsb = 2 v ref /4096 011...110 100...010 03154-a - 020 0 lsb f i gur e 2 0 . idea l t r ansfe r char act e r i stic
ad7452 rev. b | page 14 of 28 typical connection diagram f i gur e 21 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7452 f o r bo th 5 v and 3 v s u p p lies. i n this s e t u p , t h e gnd p i n is co nne c t e d t o t h e a n alog g r o u n d plan e o f t h e sys t em. the v ref p i n is co nnec t e d t o ei t h er a 2.5 v o r a 2 v decou p led r e f e r e n c e so u r c e , d e pen d in g o n th e po w e r s u p p l y , t o se t u p th e a n al og in p u t ra n g e . the co mm o n - m o d e v o l t a g e has to b e s e t u p ext e r n al ly a n d i s t h e va l u e o n w h ich t h e tw o in p u ts a r e ce n t er e d . t h e co n v er sio n r e s u l t is o u t p u t in a 16-b i t w o r d wi t h f o ur l e a d i n g z e ro s f o l l owe d by t h e m s b of t h e 1 2 - bit re su lt . f o r more det a i l s o n dr ivi n g t h e dif f er en t i a l in p u ts and s e t t in g u p t h e co mm o n m o de , r e fer t o t h e dr i v in g dif f er en t i a l i n p u ts s e c t ion. serial interface 2v/2.5v v ref ad7452 c/ p 0.1 f 3v/5v supply 0.1 f 10 f v dd v in+ v in ? sclk sdata cs gnd v ref cm* cm* v ref p-p v ref p-p 03154-a-021 *cm is the common-mode voltage. f i g u re 21. t y pic a l conne c t io n d i ag r a m analog input the a n alog in pu t o f t h e ad745 2 is f u l l y dif f er e n t i al. dif f er en t i al sig n als ha v e a n u m b er o f be n e f i ts o v er sin g le-en d e d sig n als, in cl u d in g n o is e imm u ni ty b a s e d o n t h e de vice s co mm o n - m o d e re j e c t i o n , i m prove m e n t s i n d i st or t i on p e r f or manc e, d o ubl i ng of t h e de vice s a v a i la b l e dyna mic r a n g e , an d f l exib i l i t y i n i n p u t ra n g es an d b i as p o in ts. f i gur e 22 def i n e s t h e f u l l y dif f er en t i al a n alog in p u t o f th e ad7452. v ref p-p v in+ v in ? ad7452 v ref p-p common- mode voltage 03154-a - 022 f i g u re 22. d i f f e r e nt ia l input d e f i nit i on the am pli t ude o f t h e dif f er en t i al sig n al is t h e dif f er en ce be tw e e n t h e sig n als a p p l ie d t o t h e v in+ and v inC pi ns (i .e ., v in+ C v inC ). v in+ an d v in C a r e sim u l t an e o usl y dr i v en b y tw o sig n als, e a c h o f a m p l i t ude v ref , tha t a r e 180 o u t o f p h as e . th e a m pli t ude o f t h e dif f er en t i al sig n al is t h er efo r e Cv ref to + v ref peak -t o- peak (i .e . , 2 v ref ). t h is is tr ue r e ga r d l e s s o f th e c o m mon mo d e ( c m ) . the co mm on mo de is t h e a v erag e o f t h e t w o sig n als, i . e ., (v in+ + v inC )/2, a n d is t h er efo r e t h e v o l t a g e u p on which t h e tw o in p u ts a r e ce n t e r e d . this r e su l t s in t h e sp an o f e a ch i n p u t b e i n g cm v ref /2. this v o l t a g e has to b e s e t u p ext e r n al ly , a n d i t s ra n g e va r i es wi t h v ref . a s t h e va l u e o f v ref in cr ea se s, th e co mm o n -m od e ra n g e d e cr ea se s. w h en d r i v i n g th e in p u t s w i t h a n am plif ier , t h e ac t u a l comm o n -mo d e ra n g e is det e r m i n e d b y t h e am plif ier s ou t p ut v o l t a g e s w i n g. f i gur e 23 a n d f i gur e 24 s h o w ho w th e co mm on-m o d e ra n g e typ i cal l y va r i es wi t h v ref f o r both 5 v an d 3 v p o w e r s u p p lies. the co mm on mo de m ust b e in t h is ra n g e t o guara n t e e t h e f u n c tio n al i t y o f th e ad7452. f o r ease o f use , th e co mm o n m o de can be set u p t o eq ual v ref , r e s u l t in g i n t h e dif f er en t i al sig n al b e i n g v ref cen t er e d o n v ref . w h en a con v ersio n t a k e s pl ace , t h e comm o n mo de is r e je c t e d , r e s u l t in g in a vir t ual l y n o is e - f r e e sig n al o f a m p l i t ude , Cv ref to +v ref , co rr es p o n d in g t o t h e dig i tal co des o f 0 t o 4096. v ref (v) 2.5 0 0.5 1.0 1.5 2.0 2.5 c o m m on - m od e v o l t a g e ( v ) 2.0 1.5 1.0 0.5 0 3.0 3.5 3.0 3.5 4.0 1.75v 3.25v 4.5 common-mode range 03154-a - 023 f i gure 23. input common-m ode r a ng e vs . v ref (v dd = 5 v and v ref (max) = 3.5 v ) v ref (v) 1.5 0 0.25 0.50 0.75 1.00 1.25 c o mmo n - mo d e v o l t a g e ( v ) 1.0 0.5 0 1.50 2.00 2.0 1v 2v 2.5 1.75 common-mode range 03154-a - 024 f i gure 24. input common-m ode r a ng e vs . v ref (v dd = 3 v and v ref (max) = 2 v )
ad7452 rev. b | page 15 of 28 f i gur e 25 s h o w s exa m ples o f t h e in p u t s t o v in+ and v inC fo r dif f er en t val u es o f v ref fo r v dd = 5 v . i t a l s o g i ves t h e max i m u m and mi ni m u m c o mm on- m o d e vol t ages fo r e a ch r e fer e n c e va l u e acco r d in g t o f i gur e 23. common-mode (cm) cm min = 1v cm max = 4v 2v p-p v in? v in+ reference = 2v common-mode (cm) cm min = 1.25v cm max = 3.75v 2.5v p-p v in? v in+ reference = 2.5v 03154-a - 025 f i g u re 25. e x a m pl e s of t h e a n al og inp u t s to v in+ and v in C fo r di ffer e nt v a l u es o f v ref fo r v dd = 5 v analog input structure f i gur e 26 s h o w s th e e q ui valen t cir c ui t o f th e a n alog in p u t s t r u c t ur e o f th e ad7452. th e f o ur dio d es p r o v ide es d p r o t ecti o n f o r th e a n alog i n p u ts . c a r e m u s t b e tak e n t o e n s u r e t h a t t h e a n alog i n p u t sig n als ne ver exce e d t h e s u p ply ra i l s b y m o r e than 300 mv . this c a us es th es e dio d es t o become for w ard - bi a s e d an d st ar t c o n d u c t i ng i n to t h e su b s t r a t e. t h e s e dio d es c a n cond uc t u p t o 10 ma wi t h o u t c a usin g ir r e v e rsi b le da ma g e t o t h e p a r t . t h e ca p a c i to r s , c1 in f i gur e 26, a r e typ i cal l y 4 pf a n d can p r ima r il y be a t tr ib u t ed t o p i n ca p a ci tan c e . the r e sisto r s ar e l u m p e d com p on e n ts ma de u p o f t h e on r e sist an c e o f t h e s w i t ch es. the val u e o f t h e s e r e sis t o r s is ty p i cal l y a b o u t 100 ?. th e ca p a ci t o rs c2 a r e t h e ad c s s a m p lin g ca p a c i t o rs a n d ha v e a typ i c a l ca p a c i tan c e o f 16 pf . c1 c2 r1 d d c1 c2 r1 d d v dd v dd 03154-a - 026 v in+ v in? f i g u re 26. equiv a le nt a n al og input c i rcuit convers i on p h as e switc h es o p e n ; t r ack phas e sw itc h es cl os ed f o r a c a p pl i c a t i o ns , re mov i n g h i g h f r e q u e nc y c o m p o n e n t s f r om th e a n alog i n p u t s i gn al th r o u g h th e u s e o f a n r c lo w - pa s s f i l t er o n the r e leva n t a n alog in p u t p i n s is r e co mm ended . i n a p p l ica- t i o n s w h er e ha r m o n ic dis t o r t i on an d sig n a l -t o- n o is e r a t i o a r e cr i t ica l , t h e a n a l og in p u t sh o u l d b e dr i v e n f r o m a lo w im p e d- a n c e s o ur ce . l a rg e s o ur ce im p e dan c es sig n if ican t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e ad c. this ma y ne ces s i t a t e t h e us e o f a n in p u t b u f f er a m plif ier . th e ch o i ce o f t h e o p am p is a f u n c t i on of t h e p a r t ic u l a r a p plica t io n. w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e d a n c e sh ou ld b e li mite d to lo w va l u es. the max i m u m s o u r c e i m p e d a n c e d e p e nd s o n t h e a mou n t of to t a l h a r mon i c d i stor t i on ( t h d ) t h a t c a n b e t o lera t e d . th e thd in cr eases as t h e s o ur ce i m p e dan c e i n cr e a s e s, a n d p e r f o r ma nce deg r ades. f i g u re 2 7 show s a g r a p h of t h e t h d ve r s u s t h e an a l o g i n put sig n al f r e q uen c y fo r dif f er en t s o ur ce im p e dan c es fo r v dd = 5 v . input frequency (khz) 10 100 thd (db) ?40 ?60 ? 100 277 ?20 0 t a = 25c v dd = 5v r in = 510 ? r in = 1k ? r in = 10 ? r in = 300 ? ?80 03154-a - 027 f i g u re 27. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o u r c e impedanc es for v dd = 5 v f i g u re 2 8 show s a g r a p h of t h e t h d ve r s u s t h e an a l o g i n put fr e q u e n c y f o r v dd o f 5 v 5% a n d 3 v +20%/C10%, while sa m p ling a t 555 ks ps wi t h an s c lk o f 10 mh z. i n this case , the s o ur ce im p e dance is 10 ?. 10 100 thd (db) ?60 ?65 ?90 277 ?55 ?50 t a = 25c v dd = 4.75v ?70 v dd = 5.25v v dd = 3.6v v dd = 2.7v ?75 ?80 ?85 input frequency (khz) 03154-a - 028 f i g u re 28. th d v s . a n al og input f r equ e nc y f o r 3 v and 5 v sup p ly v o lt ag es
ad7452 rev. b | page 16 of 28 drivi n g dif f erenti al i n puts dif f er en t i al op e r a t io n r e q u ir es t h a t v in + an d v in C be si m u l t a n e- o u s l y dr i v en wi t h tw o e q ual sig n als t h a t a r e 18 0 o u t o f p h as e . the co mm on mo de m ust b e s e t u p ext e r n al ly a n d has a ran g e deter m i n e d b y v ref , t h e p o we r supply , an d t h e p a r t i c u l ar am pl i - f i er us e d t o dr i v e t h e a n alog in pu ts (s e e f i gur e 23 a n d f i gur e 24). dif f er en t i a l m o des o f o p era t io n wi t h ei t h er an ac o r a dc in p u t p r o v i d e t h e b e s t th d p e r f o r ma n c e o v er a wide f r e q u e nc y r a nge . si nc e no t a l l a ppl i c a t i o ns h a v e a s i g n a l p r eco n d i ti o n ed f o r d i f f e r e n ti al o p e r a t i o n , th e r e i s o f t e n a n eed t o p e r f o r m sin g le-ende d -t o- dif f er en t i a l con v ersio n . differenti a l a m plifier an ideal m e t h o d o f a p p l yin g dif f er en tial dr i v e to th e ad7452 is t o us e a dif f er en t i al am plif ier s u ch as t h e ad81 38. this p a r t can b e us e d as a sing le-e n d e d -to- di f f er en t i a l am plif ier o r as a dif f er en t i al -t o- dif f er en t i al am pli f ier . i n b o t h cas e s, t h e a n alog in p u t needs t o b e b i p o la r . i t als o p r o v ides co mmo n -m o d e leve l shif t i ng an d b u f f er in g o f t h e b i p o la r in p u t sig n a l . f i gur e 29 s h o w s h o w the ad8138 can be us ed as a sin g le-en d ed-t o- dif f er en t i al a m plif ier . th e p o si t i v e a n d n e g a t i ve o u t p u t s o f t h e ad8138 a r e conn ec t e d t o the r e s p ec ti ve in p u ts o n the ad c via a p a ir o f s e r i es r e sis t o r s t o minimize t h e ef fe c t s o f swi t ch e d ca p a c i t a n c e on t h e f r o n t e n d o f t h e ad c s . th e r c lo w-p a s s f i l t er o n e a ch a n a l og in p u t is r e c o mmende d in a c a p plic a t io ns to r e m o v e hig h f r e q uen c y co m p onen ts o f t h e a n al og in p u t. the a r c h i t ec t u r e o f th e ad8138 r e s u l t s in o u t p u t s tha t a r e v e r y hig h ly b a lance d o v er a wide f r e q uen c y ra n g e w i t h ou t r e q u ir in g t i g h t l y ma tc he d e x te r n a l c o m p one n t s . i f t h e ana l o g i n pu t s o u r c e bein g us e d has zer o im p e dan c e, al l fo ur r e sis t o r s (r g 1, r g 2, r f 1, r f 2) s h o u ld be t h e s a me . i f , f o r exa m p l e , th e s o u r ce has a 50 ? im p e dan c e and a 50 ? t e r m ina t io n, t h e va l u e o f r g 2 s h o u ld be in cr e a s e d b y 25 ? t o b a lan c e t h i s p a ral l e l im p e da n c e o n t h e i n p u t a n d th u s e n s u r e t h a t b o th t h e po s i ti v e a n d n e g a t i v e a n a l o g in p u ts ha ve t h e s a me ga in (s e e f i gur e 29). th e o u t p u t s o f t h e a m plif ier a r e p e r f e c t l y ma t c h e d , b a lan c e d dif f er en t i al o u t p u t s of iden tical am p l i t ude , a n d a r e exac tl y 180 o u t o f p h as e . the ad8138 is s p ecif ie d wi t h +3 v , +5 v , a n d 5 v p o w e r su p p l i e s , b u t t h e b e st re su lt s are ob t a i n e d w h e n it is su p p l i e d b y 5 v . the ad81 32 is a lo w e r cos t de vic e tha t cou l d als o be us ed in t h is co nf igur a t io n w i t h slig h t dif f er en ces i n cha r ac t e r i st ics t o th e ad8138 b u t wi t h simi la r p e r f o r ma n c e and o p era t ion. external v ref (2.5v) +2.5v gnd ?2.5v 51 ? r g 1 r g 2 v ocm r f 2 r f 1 r s * r s * c* c* v in+ v in ? ad7452 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v v ref *mount as close to the ad7452 as possible and ensure high precision rs and cs are used. r s ?5 0 ? ; c ? 1nf r g 1 = r f 1 = r f 2 = 499 ? ; r g 2 = 523 ? 03154-a - 029 ad8138 f i g u re 29. u s ing t h e a d 8 1 3 8 as a si ng le -e nded- t o - d i f f e re nt ia l a m p lif ier
ad7452 rev. b | page 17 of 28 op a m p p a ir an o p a m p p a ir ca n be use d t o dir e c t l y co u p le a dif f er en t i al sig n al t o th e ad7452. the cir c ui t co nf igura t ion s sh o w n in f i gur e 30 a n d f i gur e 31 s h o w ho w a d u al o p am p can be us ed t o co n v er t a si n g le -ende d sig n al i n t o a dif f er en t i al sig n al fo r b o t h a bi p o l a r a n d u n i p o l a r i n put s i g n a l , re s p e c t i v e l y . the v o l t a g e a p plie d t o p o i n t a s e ts u p t h e co mm on- m o d e v o l t a g e . i n bo t h dia g ra m s , i t is c o nn ec t e d in so m e wa y t o t h e r e fer e n c e , b u t an y val u e i n t h e co mm o n - m o d e ra n g e can b e in p u t her e t o s e t u p th e comm on m o de . the ad8022 is a sui t ab le d u a l o p a m p t h a t co u l d b e us e d in t h is co nf igura t io n to p r o v ide dif f er en tial dr i v e t o the ad7452. c a r e m u s t b e t a k e n w h e n ch o o sin g t h e o p am p b e ca us e t h e s e le c t io n dep e nds o n t h e r e q u ire d p o w e r su p p ly a n d t h e sy ste m p e r f o r ma n c e ob je c t i v es. th e dr i v er cir c ui ts in f i gur e 30 a n d f i gur e 31 a r e o p timize d f o r dc co u p lin g a p p l ic a t io n s tha t re qu i r e opt i m u m d i s t or t i on p e r f o r m a nc e. the dif f er en t i al o p a m p dr i v er c i r c ui t in f i gur e 30 is co nf igur e d t o co n v er t and le v e l s h if t a sin g l e -e n d e d , g r o u nd-r efer en c e d (b i p ola r ) sig n al t o a dif f er en t i al sig n al cen t er e d a t t h e v ref leve l of t h e a d c . the cir c ui t conf igur a t io n sh ow n in f i gur e 31 co n v er ts a uni p ol a r , sin g le-en d e d sig n al in to a dif f er en t i al sig n al . gnd 2 v ref p-p external v ref v in+ v in? ad7452 v ref v dd v+ v? v+ v? 220 ? 220 ? 27 ? 390 ? 220 ? 20k ? 10k ? 220 ? 27 ? a 0.1 f 03154- a- 030 f i gure 3 0 . dua l o p a m p cir c ui t to co nv er t a single-ended bipo l a r s i g n a l int o a d i f f e r e nt ia l s i g n a l v ref 2 v ref p-p external v ref v in+ v in? ad7452 v ref v dd v+ v? v+ v? 220 ? 220 ? 27 ? 390 ? 10k ? 220 ? 27 ? gnd a 0.1 f 03154- a- 031 f i gure 3 1 . dua l o p a m p cir c ui t to co nv er t a single-ended uni p ol ar si gnal i n to a di ffer e nt i a l si g n a l rf tr a n sforme r i n sys t em s tha t do n o t n e ed t o be dc -co u p l e d , a n rf tra n s- fo r m er wi t h a c e n t er t a p o f fers a go o d s o l u t i o n fo r gen e ra t i n g dif f er en t i al in p u ts. f i gur e 32 s h ows h o w a t r a n sfo r m e r is us e d fo r sin g le-en d e d -t o- dif f er en t i al co n v ersio n . i t pr o v ides t h e b e n e f i t s o f o p era t in g t h e a d c i n t h e dif f er en t i a l m o de wi t h o u t c o n t r i but i ng a d d i t i on a l noi s e a n d d i s t or t i on . a n r f t r ans f or m e r a l s o has t h e b e nef i t o f p r o v iding e l e c t r ica l is ol a t io n b e t w e e n t h e sig n al s o ur ce and t h e ad c. a t r a n sfo r m e r ca n be us e d fo r m o st ac a p plic a t ion s . the ce n t er t a p is us e d t o s h if t t h e dif f er en t i al sig n a l t o t h e comm on- m o d e l e v e l r e q u ir e d ; i n t h is cas e , i t is co nne c t e d t o t h e r e fer e n c e s o t h e comm o n - m o d e le ve l is t h e val u e o f t h e r e fe r e n c e . external v ref (2 . 5 v) r r c v in+ v in? ad7452 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v v ref r 03154-a - 032 f i g u re 32. u s ing an r f t r ans f or me r t o gener a t e d i f f e r e nt i a l i n put s
ad7452 rev. b | page 18 of 28 digi tal in p u ts the dig i tal in p u ts a p p l ie d t o t h e ad7452 a r e n o t limi t e d b y t h e max i m u m r a t i ngs, w h ich lim i t t h e ana l o g limi ts . i n ste a d t h e dig i t a l in p u ts a pplie d , i . e., cs an d s c l k , c a n go to 7 v an d are not re st r i c t e d by t h e v dd + 0.3 v limi ts as on th e analog in p u t. the ma i n ad van t a g e o f t h e i n pu ts b e in g unr e s t r i c t e d t o t h e v dd + 0.3 v limi t is tha t p o w e r s u p p l y s e q u en cin g is s u es a r e av o i d e d . if cs an d sclk a r e a p plie d b e fo r e v dd , t h er e is n o r i s k o f la t c h-u p as t h er e w o uld be o n the a n alog in p u ts if a signal g r ea t e r tha n 0.3 v was a p p l ie d p r io r t o v dd . reference a n e x te r n a l re f e re nc e s o u r c e i s r e qu i r e d to supp ly t h e re f e re nc e t o th e ad7452. this r e f e r e n c e in p u t ca n ran g e f r o m 100 mv t o 3.5 v . w i t h a 5 v p o w e r s u p p l y , th e sp ecif ie d r e f e r e n c e is 2.5 v a n d t h e maxim u m r e f e r e n c e is 3.5 v . w i t h a 3 v p o w e r s u p p l y , t h e s p e c i f i e d re f e re nc e i s 2 v a n d t h e m a x i m u m re f e re nc e i s 2.2 v . i n bo th cas e s, th e r e f e r e n c e is f u n c tio n a l f r o m 100 mv . i t is im p o r t an t to en s u r e t h a t w h e n ch o o sin g t h e r e fer e n c e val u e fo r a p a r t ic u l a r a p plic a t ion, t h e maxim u m a n a l og in p u t ra n g e ( v in ma x ) is n e ver gr ea t e r th a n v dd + 0.3 v t o co m p l y wi th t h e maxim u m ra t i ngs o f t h e de vic e . the fol l o w in g t w o exa m ples calc u l a t e t h e maxim u m v ref i n p u t th a t c a n be u s ed wh e n o p era t in g the ad7452 a t a v dd o f 5 v a n d 3 v , r e s p ec ti ve l y . exampl e 1 v in max = v dd + 0.3 v in max = v ref + v ref /2 if v dd = 5 v , th en v in ma x = 5.3 v . ther efo r e 3 v ref /2 = 5.3 v v ref max = 3.5 v t h u s , wh en o p era t i n g a t v dd = 5 v , t h e val u e o f v ref ca n ran g e f r o m 100 mv t o a maxim u m val u e o f 3.5 v . w h en v dd = 4.75 v , v ref max = 3.17 v . exampl e 2 v in max = v dd + 0.3 v in max = v ref + v ref /2 if v dd = 3 v , th en v in ma x = 3.3 v . ther efo r e 3 v ref /2 = 3.3 v v ref max = 2.2 v t h u s , wh en o p era t i n g a t v dd = 3 v , t h e val u e o f v ref ca n ran g e f r o m 100 mv t o a maxim u m val u e o f 2.2 v . w h en v dd = 2.7 v , v ref max = 2 v . th e s e exa m ples s h o w t h a t t h e maxim u m r e fer e n c e a p pli e d t o th e ad7452 is dir e c t l y dep e nden t o n t h e val u e a p p l ie d t o v dd . the val u e o f t h e r e fer e n c e s e ts t h e analog in p u t s p a n and t h e c o m mon - m o d e vo lt age r a ng e. e r ror s i n t h e re f e re nc e s o u r c e r e s u l t in ga in er r o rs in th e ad7 452 tra n sf er f u n c tio n an d add to s p ecif ie d f u l l -s c a le er r o rs o n th e p a r t . a 0.1 f ca p a c i t o r sh o u ld be use d t o deco u p le th e v ref pi n to g n d . f i gur e 33 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e v ref pi n . 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7452* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f 03154-a - 033 *additional pins omitted for clarity f i g u re 33. t y pic a l v ref c o nnec t ion d i agr a m for v dd = 5 v table 5. exa m ples of suitable voltage re fere nces reference ou tpu t voltage (v) initial accu racy (%) operating current (a) ad780 2.5/3 0.04 1000 adr421 2.5 0.04 500 adr420 2.048 0.05 500 single-ended opera t i o n w h en su p p lie d wi t h a 5 v p o w e r s u p p l y , th e ad7452 ca n han- d l e a s i ng l e - e nd e d i n put . t h e d e s i g n o f this p a r t is o p timized f o r dif f er en t i al op er a t io n, s o wi t h a sin g le-e n d e d i n p u t, p e r f o r - ma nce deg r ades . l i n e a r i t y deg r ades b y 0.2 ls b typ i cal l y , t h e f u l l -s cale er r o rs deg r ade b y 1 l s b typ i cal l y , a n d ac p e r f o r ma nce i s not g u ar an te e d . t o o p er a t e t h e ad7452 in sin g le-ende d m o de , th e v in + in p u t i s co u p le d t o t h e s i g n al s o ur ce , whi l e t h e v inC in put is b i as e d t o t h e a p p r o p r i a t e v o lt a g e co r r es p o n d i n g t o t h e mids c a le co de t r a n s i - t i o n . this v o l t a g e is t h e comm on m o de , w h ich i s a f i xe d dc v o l t a g e (us u al ly t h e r e fer e n c e). the v in+ in pu t s w i n gs a r o u nd t h is va l u e an d sh o u ld h a v e a v o l t a g e sp an o f 2 v ref to ma k e us e o f t h e f u l l dyna mic ra n g e o f t h e p a r t . th e i n p u t sig n al t h er efo r e has p e ak-t o- p e a k val u es o f co mm on m o de v ref . i f t h e an a l o g i n put i s u n i p o l ar , an op am p i n a non i n v e r t i ng u n it y ga in co nf igur a t i o n can b e us e d to dr ive t h e v in+ pi n . b e c a u s e t h e ad c op era t es f r o m a sin g le s u p p ly , i t is n e ce s s a r y t o le v e l s h i f t gr o u n d -based b i po la r si gnals t o co m p l y wi th th e i n p u t r e q u ir em en ts. an o p a m p can b e co nf igur ed t o r e s c ale an d l e v e l s h i f t t h e gr o u n d - b a s e d b i po l a r s i gn al so i t i s c o m p a t i b l e wi th th e s e lec t e d in p u t ra n g e o f the ad7452 (s ee f i gur e 34).
ad7452 rev. b | page 19 of 28 external v ref (2.5v) r v in+ v in ? ad7452 5v 2.5v 0v v ref + 2.5v 0v ? 2.5v v in r r 0.1 f r 03154-a - 034 f i gure 34. a p plying a b i polar s i ng l e -e nded input to the a d 7 452 serial interface f i g u r e 2 s h o w s a d e ta iled tim i n g d i a g ra m f o r th e se r i al in t e rface o f th e ad7452. the s e r i al c l o c k p r o v ides the con v ersio n c l o c k a n d also co n t r o ls th e tra n s f e r o f da ta f r o m t h e devi ce d u ri n g co n v ersio n . cs ini t ia t e s t h e con v ersio n p r o c es s and f r a m es t h e da ta tra n s f e r . t h e fallin g ed g e o f cs p u t s th e tra c k - a n d - h o ld i n to ho l d mo d e an d t a ke s t h e bu s out of t h re e - st ate. t h e a n a l o g in p u t is s a m p le d an d t h e con v e r sio n is ini t i a t e d a t t h is p o in t. the con v ersio n r e q u ir es 16 scl k c y cles t o co m p let e . on ce 13 s c lk f a l l in g edg e s ha ve o c c u r r ed , th e t r ac k-and-h o ld g o es bac k in t o t r ac k o n t h e n e xt sclk r i sin g edg e , as sh o w n a t p o in t b in f i gur e 2. on t h e 16 th sclk fal l in g edg e , th e s d a t a lin e go es b a ck i n t o t h r e e- s t a t e . i f t h e r i sin g e d ge o f cs oc cu r s b e fo r e 16 sclks ha v e e l a p s e d , t h e con v ersion is t e r m ina t e d a n d t h e sd a t a li ne g o es b a ck i n t o t h r e e-s t a t e . the con v ersio n r e s u l t f r o m th e ad7452 is p r o v ided on t h e s d a t a o u t p ut as a s e r i a l d a t a st r e a m . th e b i ts a r e clo c k e d o u t o n the fal l in g e d g e o f th e s c lk in p u t. the da ta s t r e am o f th e ad7452 co n s is ts o f f o ur leadin g zer o s f o l l o w ed b y 12 b i ts o f c o n v e r s i on d a t a prov i d e d m s b f i r s t . t h e output c o d i ng i s t w o s co m p lem e n t . sixt e e n s e r i al cl o c k c y cles a r e r e q u ir e d t o p e r f o r m a con v ersio n a n d access da t a f r o m th e ad74 52. cs go in g lo w p r o v ides t h e f i rst le adin g zero to b e r e ad in by t h e micr o c on t r ol ler o r ds p . the r e ma inin g da t a is t h e n clo c k e d o u t on t h e subs e q ue n t s c l k f a l l i n g e d ge s b e g i n n i ng w i t h t h e s e c o nd l e a d i n g z e ro . th us, t h e f i rs t f a l l in g clo c k e d ge o n t h e s e r i al cl o c k p r o v ides t h e s e con d le adin g zer o . th e f i nal b i t i n t h e da t a t r an sfer is valid o n th e 16 th fal l in g e d g e , ha vin g b een c l o c k e d o u t o n the p r e v io us (15 th ) fal l in g edg e . on ce t h e con v ersio n is com p let e an d t h e da ta has b e en acces s e d a f t e r t h e 16 clo c k c y cles, i t is im p o r t an t t o en s u r e t h a t b e for e t h e n e xt con v ersio n is ini t i a t e d , en o u g h t i me is lef t t o m e e t t h e acq u isi t ion, and q u iet t i m e sp e c if ica t ion s (s e e t h e t i mi n g e x a m ple). i n a p plic a t io n s wi t h a slo w er sclk, i t ma y b e p o ssi b le t o r e a d in da ta o n ea ch scl k ri s i n g ed g e , i . e . , th e f i r s t ri s i n g ed g e o f sc lk af te r t h e cs fa l l in g e d ge w o u l d h a ve t h e le a d in g ze r o p r o v ide d an d t h e 1 5 th sclk edge w o uld ha v e d b 0 p r o v ided . timing example ha v i n g f sc l k = 10 mh z and a t h r o ug h p u t ra t e o f 555 ks ps g i ves a c y cl e t i me of 1/ th r o u g h p u t = 1/555,000 = 1.8 s a c y cle co n s ists o f t 2 + 12.5(1/ f sclk ) + t ac q = 1.8 s ther efo r e , if t 2 = 10 n s 10 n s + 12.5(1/10 mh z) + t ac q = 1.8 s t ac q = 540 n s this 540 n s s a tisf ies th e r e q u ir em en t o f 290 n s f o r t ac q . fr o m fi g u r e 3 5 , t ac q co m p r i s e s 2.5(1/ f sclk ) + t 8 + t qu i e t wher e t 8 = 35 n s . this al lo ws a val u e o f 255 n s f o r t qu i e t , sa ti s f yi n g t h e mi n i m u m r e q u i r em en t o f 60 n s . t 2 t 8 t 6 t 5 t convert cs sclk 12 3 4 5 1 3 1 4 1 5 1 6 03154-a - 035 12.5(1/f sclk ) t acquisition 1/throughput t quiet 10ns f i gure 35. s e ri al inter f ace ti ming e x a m pl e
ad7452 rev. b | page 20 of 28 modes of operation the m o de o f o p era t io n o f t h e ad7452 is s e lec t e d b y co n t r o l l in g t h e log i c s t a t e of t h e cs sig n al d u r i n g a con v ersion. th er e a r e tw o p o ssib le mo des o f o p er a t ion, n o r m a l and p o w e r - do wn. t h e p o in t a t w h ich cs is p u l l ed hig h a f t e r th e co n v er sio n has been ini t ia t e d deter m in es w h et h e r o r n o t t h e ad7452 en t e rs t h e p o w e r - do w n mo de. simi la rly , if a l r e ad y in p o wer - do w n , cs co n t r o ls whet h e r t h e de vice r e t u r n s t o n o r m al o p era t ion o r r e ma in s i n p o wer - do wn. th es e m o de s o f o p era t io n a r e desig n e d to prov i d e f l e x ibl e p o we r m a n a ge me n t opt i ons . t h e s e opt i o n s ca n be ch os en to o p timize t h e p o w e r dis s i p a t io n/thr o ug h p u t ra t e ra t i o f o r d i f f er in g a p p l ica t io n r e q u ir em en ts. normal m o de this m o de is in t e nde d fo r fast e s t t h r o ug h p ut ra t e p e r f o r ma n c e . the us er do es no t ha v e t o w o r r y a b o u t an y p o w e r - u p t i m e s wi t h th e ad7452 r e ma inin g f u l l y p o w e r e d u p al l the tim e . f i gur e 3 6 s h o w s t h e g e n e r a l dia g ra m o f t h e ad7452 s o p era t io n in this mo d e . t h e c o n v e r s i on i s i n it i a te d on t h e f a l l i n g e d ge of cs , a s d e sc ri bed in th e se ri al i n t e rf a c e secti o n . t o e n s u r e th a t th e pa r t re m a i n s f u l l y p o we re d up , cs m u s t r e ma in lo w un til a t least 10 sclk fal l i n g e d g e s ha v e el a p s e d a f t e r t h e fal l ing e d g e o f cs . if cs i s b r o u gh t h i gh a n y tim e a f t e r th e 1 0 th scl k fal l in g e d ge , but b e f o re t h e 1 6 th s c l k f a ll in g ed g e , th e pa r t r e m a i n s po w e r e d u p b u t t h e con v ersio n is t e r m ina t e d and s d a t a g o es b a ck in to t h r e e-s t a t e . sixte e n s e r i al clo c k c y cles a r e r e q u ir e d t o com p let e t h e con v ersio n a n d access t h e c o m p let e con v ersio n r e s u l t . cs ma y idle hig h u n til t h e n e xt con v ersio n o r ma y idle lo w un til s ome t i me pr i o r to t h e ne x t c o n v e r s i on . o n c e a d a t a t r a n s f e r i s c o m p l e t e , i . e . , w h e n s d a t a h a s r e t u r n e d t o t h r e e - s t a t e , a n o t h e r co n v ersio n can be ini t ia t e d a f t e r th e q u iet tim e , t qu iet , h a s el a p s e d b y ag ai n b r i n g i ng cs lo w . 11 0 cs sclk sd a t a 16 4 leading zeros + conversion result 03154-a - 036 f i g u re 36. no r m a l m o de o p er at io n power-down mode this m o de is in t e nde d fo r us e in a p pli c a t io n s w h er e slo w er th r o u g h p u t ra t e s a r e r e q u i r ed ; ei th e r t h e a d c i s po w e r e d d o wn b e t w e e n e a c h c o n v e r s i on , or a s e r i e s of c o n v e r s i ons m a y b e p e r f o r m e d a t a high thr o ugh p u t ra t e and t h e ad c is then po w e r e d d o w n f o r a r e l a ti v e l y l o n g d u r a ti o n b e t w e e n th e s e b u rs ts o f s e veral co n v ersio n s. w h en the ad745 2 is in p o w e r - do wn m o de, a l l a n a l o g cir c ui t r y is p o w e r e d do w n . t o e n ter p o w e r - do wn mo de , t h e con v ersio n p r o c es s m ust be in t e r r u p t e d by br i n g i n g cs high an y w h e r e a f t e r th e seco nd fal l i n g edge o f sclk, and befor e th e 10 th f a l l i n g e d ge of s c l k , a s s h ow n i n f i gur e 37. 1 10 cs sclk sdata three-state 2 03154-a - 037 f i gure 37. enter i ng p o w e r - d o wn mod e on ce cs h a s been b r o u gh t hi gh in t h i s w i n d ow of s c l k s , t h e p a r t en t e rs p o w e r - do wn, t h e con v ersio n t h a t was ini t i a te d b y t h e fal l in g e d ge o f cs is t e r m ina t e d , a n d sd a t a go es b a ck i n t o t h r e e-s t a t e . th e t i me f r o m t h e r i sin g e d g e o f cs to sd a t a t h r e e-s t a t e ena b le d is ne v e r g r e a t e r t h a n t 8 (r efer t o t h e t i mi n g s p e c if ic a t io n s ). i f cs i s b r o u gh t h i gh be f o r e th e s e c o n d s c lk fa l l in g e d ge , t h e p a r t r e ma in s in n o r m a l m o de and do es n o t p o w e r do wn. t h is a v o i ds a ccid e n t a l p o w e r - do w n d u e to g l i t ches on t h e cs lin e . i n ord e r to e x it t h i s mo d e of op e r a t i o n an d p o we r up t h e ad7452 a g ain, a d u mm y con v ersio n is p e r f o r m e d . on t h e fal l in g edg e o f cs , t h e d e v i c e b e g i ns to p o we r up an d c o n t i n u e s t o p o w e r u p as lo n g as cs is h e ld l o w un til a f t e r t h e fal l in g edge of t h e 1 0 th sclk. th e de vice is f u l l y p o w e r e d u p a f t e r 1 s has e l a p s e d an d , as s h own in f i gur e 38, valid da t a r e s u l t s f r o m the ne x t c o n v e r s i on . if cs i s b r o u gh t h i gh be f o r e th e 1 0 th fal l in g e d ge o f sclk, t h e ad7452 a g ain go es bac k in t o p o w e r - do wn. this a v o i ds acc i - den t al p o w e r - u p d u e t o gli t ch es o n the cs lin e o r a n inad v e r t en t b u rs t o f eig h t s c lk c y cles whi l e cs is lo w . s o al tho u gh the de vice ma y begin t o p o w e r u p o n the fal l in g e d ge o f cs , i t ag ai n p o w e r s do wn o n the r i sin g edge o f cs as lo n g as i t o c c u r s bef o r e th e 10 th s c lk f a l l in g e d ge .
ad7452 rev. b | page 21 of 28 power-up time the p o w e r - u p t i me o f th e ad7 452 is typ i cal l y 1 s, whic h m e an s tha t wi t h a n y sclk f r eq uen c y u p t o 10 mh z, o n e d u mm y c y cle is alwa ys s u f f i cien t t o al lo w t h e de vice t o p o w e r u p . on c e t h e d u mm y c y cle is co m p let e , t h e ad c is f u l l y p o w e r e d u p an d t h e i n p u t sig n a l wi l l b e ac q u ir e d p r o p erly . th e qu i e t t i me, t qu iet , m u st st i l l b e a l l o we d f r om t h e p o in t a t w h ic h t h e b us g o es b a ck in t o t h r e e-st a t e a f t e r t h e d u mm y con v ersion t o th e n e xt fal l in g edg e o f cs . w h en r u nnin g a t t h e maxim u m thr o ug h p u t ra t e o f 555 ks ps, th e ad7452 p o w e rs u p a n d acq u ir es a sig n al wi thin 0.5 ls b in one d u m m y c y cl e. w h e n p o we r i ng up f r om t h e p o we r - d o w n m o d e wi t h a d u mm y c y cle, as i n f i gur e 38, t h e t r ack-and- h o ld , w h ich was i n h o ld m o de w h i l e t h e p a r t was p o w e r e d do w n , re t u r n s to t r ack mo d e af te r t h e f i rst s c l k e d ge t h e p a r t re c e ive s af te r t h e f a l l i n g e d ge of cs . this is sh own a s p o i n t a in f i gur e 38. al th o u g h a t a n y sclk f r eq uen c y o n e d u mm y c y c l e is s u f f icien t to p o w e r u p t h e de vice and ac quir e v in , it d o e s not ne c e ss ar i l y m e an t h a t a f u l l d u mm y c y cle o f 16 sclks m ust a l wa y s ela p s e to p o w e r u p t h e de vice and ac quir e v in f u l l y ; 1 s is s u f f i cien t to p o w e r u p t h e de vice and ac q u ir e t h e in pu t sig n al. f o r exa m ple , if a 5 mh z scl k f r e q uen c y is a pplie d t o t h e ad c, th e c y c l e tim e is 3.2 s (i .e ., 1/(5 mh z) 16). i n o n e d u mm y c y c l e , 3.2 s, th e p a r t is p o w e r e d u p a n d v in full y a c q u i r ed . h o w e v e r , a f t e r 1 s wi t h a 5 mh z sclk, o n l y f i v e sclk c y c l es wou l d h a ve el a p s e d. a t t h i s st ag e, t h e a d c i s f u l l y p o we re d up a n d t h e si gn al acq u i r ed . s o in t h i s ca s e , cs c a n be b r o u gh t hi gh af te r t h e 1 0 th s c l k f a l l i n g e d ge an d b r ou g h t l o w ag ai n af te r a ti m e , t qu iet , t o ini t ia t e t h e con v ersio n . w h en p o w e r s u p p l ies a r e f i rs t a p p l ied t o t h e ad7452, th e ad c m a y p o we r up e i t h e r i n p o we r - d o w n mo d e or i n nor m a l mo d e . b e c a u s e of t h i s , i t i s b e st to a l l o w a d u m m y c y cl e to el a p s e to e n su re t h e p a r t i s f u l l y p o we re d up b e f o re atte m p t i ng a v a l i d co n v ersio n . l i k e wis e , if t h e us e r wa n t s t h e p a r t t o p o w e r u p in p o w e r - do wn mo de , t h e d u mm y c y cle ma y b e us e d t o en s u r e t h e de vice is in p o wer - do wn b y exe c u t in g a c y cle such as t h e on e s h own in f i gur e 37. on ce s u p p lies ar e a p p l ie d t o the ad7452, t h e p o w e r - u p tim e is th e sam e as tha t when p o w e r i n g u p f r o m p o w e r - do wn m o de . i t tak e s a p p r o x ima t e l y 1 s t o po w e r u p full y i f t h e pa r t po w e r s u p i n nor m a l mo d e . i t i s not ne c e s s ar y to w a it 1 s b e fore e x e c ut i n g a d u mm y c y cle t o en s u r e t h e de sir e d m o de o f op era t ion. i n s t e a d , t h e d u m m y c y c l e ca n o c cur d i r e ctl y a f t e r po w e r is s u p p lie d t o t h e ad c. i f t h e f i rs t valid con v ersi o n is p e r f o r m e d dir e c t l y a f t e r the d u mm y con v ersio n , ca r e m u s t be ta k e n t o en s u r e tha t ade q ua t e ac q u isi t io n tim e has b e en al lo w e d . a s m e n t io n e d e a r l ier , wh en p o w e r i n g u p f r o m th e p o w e r - do wn mo d e , t h e p a r t re tu r n s to t r a c k mo d e up o n t h e f i r s t s c l k e d ge a p plie d a f t e r t h e fa l l in g e d ge o f cs . h o w e v e r , w h e n t h e a d c p o we rs up i n i t i a l l y af te r suppl i e s are a p pl i e d, t h e t r a c k - a n d - hol d is a l r e ad y in t r a c k m o de . this m e an s if (assu min g on e h a s t h e f a c i l i t y to mon it or t h e a d c s u pply c u r r e n t ) t h e a d c p o we r s up i n t h e d e s i re d mo d e of op e r a t i o n , an d t h u s a du m m y c y cl e i s not re qu i r e d to ch ange t h e mo d e , an d a d u m m y c y cl e i s not r e q u i r ed t o p l ace th e tra c k - a n d - h o ld in t o tra c k m o de . cs sclk sdata 1 10 1 6 1 1 0 1 6 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up 03154-a - 038 f i g u re 38. e x it ing p o wer - d o wn m o de
ad7452 rev. b | page 22 of 28 power vs. throughput rate b y usin g t h e p o w e r - do wn m o de o n t h e ad745 2 when n o t con- v e r t in g, t h e a v er a g e p o w e r co n sum p t ion o f t h e ad c de cr e a s e s a t lo w e r t h r o ug h p u t r a t e s. f i gu r e 39 s h o w s h o w , as t h e t h r o ug h- p u t ra te is r e d u c e d , the device r e m a in s in i t s p o w e r - do wn s t a t e lo n g er a n d t h e a v era g e p o w e r con s um pt io n is r e d u ce d acco r d in g l y . i t sh o w s this f o r both 5 v an d 3 v p o w e r s u p p lies. f o r exa m p l e , if th e ad7452 is op era t e d in con t in uo us s a m p ling m o de wi t h a thro ug h p u t r a t e o f 100 ks ps and an scl k o f 10 mh z, and t h e de vic e is place d in p o w e r - do w n m o de b e tw e e n co n v ersio n s, t h e p o w e r co n s um p t io n is c a lc u l a t e d as fol l o w s: p o w e r dis s i p a t i o n d u ri n g n o r m a l op e r a t i o n = 7.25 mw max ( fo r v dd = 5 v) i f t h e p o wer - u p t i me is on e d u mm y c y cle ( 1 .06 s if cs is b r o u gh t hi gh a f t e r th e 1 0 th sclk fal l in g e d g e and th en b r o u gh t lo w a f t e r th e q u i e t tim e ) a n d th e r e m a i n in g co n v e r s i o n tim e i s a n o t h e r c y c l e , i . e . , 1.6 s, th e ad7452 can b e s a id t o dis s i p a t e 7.25 mw f o r 2. 66 s ? d u r i n g eac h co n v er sio n c y c l e . i f th e thr o ug h p u t ra t e = 100 ks ps, th e c y c l e tim e = 10 s and t h e a v era g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle is (2.66/10) 7.25 mw = 1.92 mw f o r th e sa m e sce n a r i o , i f v dd = 3 v , t h e p o w e r d i ssi p a t ion d u r i ng n o r m al o p er a t io n is 3.3 mw max. the ad7452 can n o w be s a id to dis s i p a t e 3.3 mw f o r 2.66 s ? d u r i ng e a ch c o n v ers i on c y cl e. the a v er a g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle wi t h a thr o ug h p u t ra t e o f 100 ks ps is th er ef o r e (2.66/10) 3.3 mw = 0.88 mw this is h o w t h e p o w e r n u m b ers in f i gur e 39 a r e ca lc u l a t e d . f o r t h r o ug h p u t ra t e s ab o v e 320 ks ps, i t is r e commende d t h a t th e se r i al c l oc k f r eq u e n c y be r e d u ced f o r o p tim u m po w e r pe rf o r m a n c e . ? this f i gure ass u mes a v e ry s h ort time t o en t e r power- d o w n m o de. th i s i n crea ses a s t h e bu r s t o f c l ock s u s e d t o en t e r t h e powe r- do wn m o de i s i n crea sed. throughput (ksps) 100 0 350 p o we r (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v 03154-a - 039 f i gure 39. p o wer v s . thro ughput r a te f o r p o wer - d o w n m o de microproc e ssor and dsp inter f acing the s e r i al in ter f ace o n t h e ad7 452 al lo ws th e p a r t t o be dir e c t l y co nne c t e d t o a r a n g e o f dif f er en t micr o p r o ces s ors. this s e c t io n exp l a i n s h o w t o in t e r f ace t h e ad7452 wi th s o m e o f t h e m o r e c o m mon m i c r o c on t r o l l e r and d s p s e r i a l i n te r f a c e proto c o l s . ad7452 to adsp-21xx t h e ads p -21xx fa m i l y o f ds p s is in t e r f ace d dir e c t l y t o th e ad7452 wi t h o u t a n y g l ue log i c r e q u ir ed . the s p or t con t r o l r e g i ster sh ou ld b e s e t u p as fol l o w s: t f sw = rfsw = 1, al t e r n a t e f r a m in g invrfs = inv t fs = 1, a c ti v e lo w f r a m e s i g n al d t yp e = 00, rig h t-j u s t if y da ta s l en = 1111, 16-b i t d a t a -w o r ds i s c l k = 1 , i n t e rn al se ri al cl oc k t f sr = r f sr = 1 , fr ame e v e r y w o rd irfs = 0 itfs = 1 t o im p l em en t p o w e r - do wn m o de , s l en s h o u l d b e s e t t o 1001 to issu e an 8 - bi t s c l k b u rst . the co n n e c t i on di ag r a m is sh ow n in f i gur e 40. the a d s p -21x x h a s th e t f s a n d r f s o f th e s p o r t ti e d t o g e t h e r , w i t h t f s set as a n o u t p ut and rfs s e t as a n i n p u t. th e dsp o p era t es in al t e r n a t e f r a m ing m o de and t h e s p o r t con t r o l r e g i s t er is s e t u p as des c r i b e d . the f r a m e sy n c hr o n iza t ion sig n al g e n e r a t e d on th e t f s i s ti e d t o cs a n d , as wi th a l l si gn al p r oces si n g a p plic a t ion s , e q uidist an t s a m p li n g is ne cess a r y . h o w e v e r in t h is exa m ple , t h e t i m e r i n t e r r u p t is us e d t o co n t r o l t h e s a m p li n g ra te o f th e ad c; u n der cer t a i n condi t ion s , eq uidis t a n t s a m p lin g ma y n o t be a c h i ev ed .
ad7452 rev. b | page 23 of 28 ad7452* adsp-21xx* sclk dr rfs tfs sclk sdata cs 03154-a -040 *additional pins removed for clarity f i g u re 40. inte r f a c i n g to t h e a d s p - 21x x the t i m e r r e g i s t ers, fo r e x a m ple , a r e lo ade d wi t h a val u e t h a t p r o v ides a n in te r r u p t a t t h e r e quir e d s a m p le in ter v a l . w h e n a n in t e r r u p t is r e ce i v e d , a v a l u e is t r a n smi t t e d wi t h tfs/dt (ad c co n t r o l w o r d ). the tfs is us e d t o co n t r o l t h e rfs a n d t h er efo r e th e r e a d i n g o f da ta . th e f r eq u e n c y o f th e se ri al cloc k i s se t in t h e sc lkd i v reg i s t er . w h en t h e in s t r u c t io n t o t r a n smi t wi t h tfs is g i v e n ( i .e., ax0 = t x 0), t h e st a t e o f t h e s c lk is ch e c k e d . the ds p wa i t s un t i l t h e scl k has g o ne hig h , lo w , a n d hig h ag ai n b e fore t h e t r ans m i s s i on s t ar t s . i f t h e t i me r an d s c l k val u es a r e ch os e n s u ch t h a t t h e i n s t r u c t io n t o t r a n smi t o c c u rs o n o r n e a r th e r i sin g edg e o f sclk, th e da t a ma y be tra n smi t t e d o r i t ma y wai t u n t i l t h e n e xt clo c k e d ge. f o r exa m p l e , th e ads p -2111 has a mas t er c l o c k f r eq uen c y o f 16 mh z. i f t h e sclkd i v r e g i st er is lo ade d wi t h t h e val u e 3, a n sclk o f 2 mh z is o b ta ined an d eig h t mas t er cl o c k p e r i o d s e l a p s e fo r e v er y sclk p e r i o d . i f t h e t i mer r e g i s t ers a r e lo ade d wi t h t h e val u e 8 03, 100.5 sclks o c c u r betw een in t e r r u p ts and subs e q u en t l y b e tw e e n t r a n smi t in st r u c t io n s . th is si t u a t ion r e su l t s in n o n e quidist a n t s a m p li n g b e c a us e t h e t r a n smi t in st r u c t io n is o c c u r r i n g o n a n sclk e d ge . i f t h e n u m b er o f sclks b e tw e e n in t e r r u p ts is a w h ole in teger f i gur e o f n, e q uidist a n t s a m p lin g is im p l e m en t e d b y t h e ds p . ad7452 to tms320c5x/c5 4 x the s e r i al in ter f ace o n t h e t m s 320c5x/c54x us es a co n t in uo u s s e r i al c l o c k and f r a m e sy n c hr o n iza t io n sig n als t o syn c hr o n ize t h e da t a t r an sfer o p era t io n s wi t h p e r i ph eral de vices li k e t h e ad7452. th e cs in p u t a l lo ws e a s y in t e r f acin g b e tw e e n t h e t m s320c5x/c54x a n d t h e ad7452 wi t h o u t an y g l ue log i c r e q u ir ed . th e s e r i al p o r t o f th e t m s320c5x/c54x is s e t u p t o o p era t e in b u r s t m o de wi t h in t e r n al clkx (t x s e r i al c l o c k) an d fsx (t x f r a m e syn c ). th e s e r i al po r t co n t r o l r e gis t er (s pc) m ust ha v e t h e f o l l o w in g set u p: fo = 0, fs m = 1, m c m = 1, a n d t x m = 1. th e fo r m a t b i t, fo , ma y b e s e t t o 1 t o s e t t h e w o r d len g t h to eig h t b i ts i n o r der t o im ple m en t t h e p o w e r - do wn m o de on t h e ad7452. th e c o nn ec t i o n dia g r a m is sh o w n in f i gur e 41. i t s h o u l d b e n o t e d t h at f o r s i g n a l p r o c e s s i n g ap p l i c at i o n s , i t i s i m pe ra ti v e th a t th e f r a m e s y n c hr o n i z a t i o n s i gnal f r o m th e t m s320c5x/c54x p r o v ides eq uidis t an t s a m p lin g . ad7452* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr 03154-a - 041 *additional pins removed for clarity f i g u re 41. inte r f a c i n g to t h e tm s 3 2 0 c 5 x / c5 4x ad7452 to ds p56xxx the co nn ec tion dia g ra m in f i g u r e 42 s h o w s h o w the ad7452 ca n be conn ec t e d t o the ss i (sy n c h r o n o us s e r i a l in t e r f ace) o f th e ds p56xxx fa m i l y o f ds p s f r o m m o t o r o la . t h e ss i is op e r a t e d i n s y n c h r onou s mo d e ( s y n bit i n c r b = 1 ) w i t h in t e r n al l y g e nera t e d 1-w o r d f r a m e sy n c f o r bo t h t x and rx (b i t s fs l1 = 0 and fs l0 = 0 in crb). s e t t h e wo r d len g th t o 16 b y s e t t in g bi ts w l 1 = 1 an d wl0 = 0 in cra. t o im p l em en t p o w e r - do wn mo de o n t h e ad7 452, th e w o r d len g th can be c h a n g e d t o eig h t b i ts b y s e t t in g b i ts w l 1 = 0 and w l 0 = 0 in cra. i t sh o u ld be n o te d t h a t for sig n al p r o c es sin g a p p l ica t io n s , i t is i m p e r a t i v e t h a t t h e f r am e sy n c hr o n iz a t ion sig n a l f r o m t h e ds p56xxx p r o v id es eq uid i s t an t sa m p lin g . ad7452* dsp56xxx* sclk srd sr2 sclk sdata cs 03154-a - 042 *additional pins removed for clarity f i g u re 42. inte r f a c i n g to t h e ds p 56x x x
ad7452 rev. b | page 24 of 28 application hints grounding and layout the printed circuit board that houses the ad7452 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place, a star ground point established as close as possible to the gnd pin on the ad7452. avoid running digital lines under the device because this couples noise onto the die. the analog ground plane should be allowed to run under the ad7452 to avoid noise coupling. the power supply lines to the ad7452 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, place them as close to the device as possible. evaluating the ad7452s performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7452 evaluation board, as well as many other analog devices evaluation boards ending with the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7452. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7452. for more information, see the ad7452 application note that accompanies the evaluation kit.
ad7452 rev. b | page 25 of 28 outline dimensions 13 5 6 2 8 4 7 2. 9 0 bs c pin 1 1. 6 0 bs c 1. 95 bs c 0. 65 bs c 0. 3 8 0. 2 2 0. 15 m a x 1. 3 0 1. 1 5 0. 9 0 sea t i n g pl a n e 1. 4 5 m a x 0. 22 0. 08 0. 60 0. 45 0. 30 8 4 0 2. 80 b s c compliant to jedec standards mo-178ba f i g u re 43. 8-l e ad s m a l l o u t l i n e t r ans i s t or p a ck ag e [so t - 23] (r t - 8) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge linearity error (lsb) 1 package option 2 brand i ng ad7452brt-r2 C40c to +85c 1 rt-8 c07 ad7452brt-re e l 7 C40c to +85c 1 rt-8 c07 eval-ad7452c b 3 evaluation bo ar d eval-control brd2 4 controll er boar d 1 linearity error here re fer s to integral n o nlinearity error. 2 rt = sot-23. 3 this can be us ed a s a s t and a l o ne e v aluatio n bo ard o r in conjunct i o n with the e v al uatio n bo ard co ntro l le r f o r e v al ua tio n /d e m o n s tration purpose s . 4 eva l ua t i on boa r d c o n t r oll e r. th i s board is a comp l e te unit al lo wi n g a p c t o co n t r ol a n d c o m m u n i ca t e wi t h a ll an a l o g d e vi ces e valuation boards en di n g i n t h e cb designator. for a complete eva l ua tion kit, you need to order the adc evaluation board, i.e., ev al -ad7452cb, the eval-control br d2, and a 12 v ac trans f o rmer. see the see the ad7452 applicat ion note that accompanie s the evaluation kit fo r more information.
ad7452 rev. b | page 26 of 28 notes
ad7452 rev. b | page 27 of 28 notes
ad7452 rev. b | page 28 of 28 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03154C0 C 2/04(b)

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